/* SPDX-License-Identifier: GPL */
/*
 * Copyright (C) 2023 Phytium Technology Co., Ltd.
 */
#ifndef __PHYTIUM_NPU_LEOPARD_NEW_REG_H__
#define __PHYTIUM_NPU_LEOPARD_NEW_REG_H__

#define NPU_SYS_CLK_STATUS				(0x0888U)
#define NPU_SYS_MWDT					(0x08C8U)
#define NPU_SYS_HWDT					(0x08D0U)
#define NPU_SYS_RTMC					(0x08D8U)
#define NPU_SYS_RTMD					(0x08E0U)
#define NPU_SYS_CLK_STATUS0				(0x0808U)
/*
 * Register NPU_PERF
 */
#define NPU_PERF_READ					(0x0A80U)
#define NPU_PERF_WRITE					(0x0A88U)
#define NPU_PERF_WRITE_DS				(0x0A90U)
#define NPU_PERF_READS					(0x0A98U)
#define NPU_PERF_WRITES					(0x0AA0U)
#define NPU_PERF_READ_IS				(0x0AA8U)
#define NPU_PERFWRITE_IS				(0x0AB0U)
#define NPU_PERF_RD_BS1					(0x0AB8U)
#define NPU_PERF_WR_BS1					(0x0AC0U)
#define NPU_PERF_RD_BS2					(0x0AC8U)
#define NPU_PERF_WR_BS2					(0x0AD0U)
#define NPU_PERF_RD_BS3					(0x0AD8U)
#define NPU_PERF_WR_BS3					(0x0AE0U)
#define NPU_PERF_RD_BS4					(0x0AE8U)
#define NPU_PERF_WR_BS4					(0x0AF0U)
#define NPU_PERF_RESET					(0x0AF8U)
#define NPU_PERF_ENABLE					(0x0A00U)
#define NPU_SYS_MMU_STATUS				(0x0A08U)

#define NPU_MDBG_S1					(0x0A10U)
#define NPU_MDBG_S2					(0x0A18U)
#define NPU_MDBG_IDLE					(0x0A20U)
#define NPU_MDBG_STATUS3				(0x0A28U)
#define NPU_MDBG_FAULT_STOP_STATUS			(0x0A30U)
#define NPU_MDBG_STATUS_DEBUG				(0x0A38U)
#define NPU_OUTSTANDING_READ				(0x0A40U)
#define NPU_PAGE_FAULT_STALL				(0x0A48U)

//SLC REG
#define NPU_CACHE_RESET					(0x0A50U)
#define NPU_CACHE_REQ_CNT_EN				(0x0A58U)
#define NPU_CACHE_CMDREQ_RD				(0x0A60U)
#define NPU_CACHE_CMDBCK_REQ_WR				(0x0A68U)
#define NPU_CACHE_CMDCRC_REQ_WR				(0x0A70U)
#define NPU_CACHE_CMDDBG_REQ_WR				(0x0A78U)
#define NPU_CACHE_CMDREQ_FENCE				(0x0B80U)
#define NPU_CACHE_IREQ0_RD				(0x0B88U)
#define NPU_CACHE_MM_REQ_RD				(0x0B90U)
#define NPU_CACHE_MM_REQ_WR				(0x0B98U)
#define NPU_CACHE_CREQ_RD				(0x0BA8U)
#define NPU_CACHE_AREQ_RD				(0x0BB0U)
#define NPU_CACHE_OPK_REQ_WR				(0x0BB8U)
#define NPU_CACHE_CMDREQ_RD_WORD			(0x0BC0U)
#define NPU_CACHE_CMDBCK_REQ_WR_WORD			(0x0BC8U)
#define NPU_CACHE_CMDCRC_REQ_WR_WORD			(0x0BD0U)
#define NPU_CACHE_CMDDBG_REQ_WR_WORD			(0x0BD8U)
#define NPU_CACHE_CREQ_FENCE_WORD			(0x0BE0U)
#define NPU_CACHE_IREQ0_RD_WORD				(0x0BE8U)
#define NPU_CACHE_MM_REQ_RD_WORD			(0x0BF0U)
#define NPU_CACHE_MM_REQ_WR_WORD			(0x0BF8U)
#define NPU_CACHE_CREQ_RD_WORD				(0x0B08U)
#define NPU_CACHE_AREQ_RD_WORD				(0x0B10U)
#define NPU_CACHE_OPK_REQ_WR_WORD			(0x0B18U)
#define NPU_CACHE_MMU_REQ_RD				(0x0B20U)
#define NPU_CACHE_MMU_REQ_RD_WORD			(0x0B28U)
#define NPU_CACHE_EWO_REQ_RD				(0x0B30U)
#define NPU_CACHE_EWO_REQ_RD_WORD			(0x0B38U)
#define NPU_FIFO_WORD_COUNT				(0x0B40U)

#define NPU_SYS_CLK_CTRL				(0x2880U)
#define NPU_SYS_BUS_RESET_CTRL				(0x2888U)
#define NPU_SYS_RESET_CTRL				(0x2890U)
#define NPU_SYS_CMDMH_CONTROL				(0x2898U)
#define NPU_SYS_IMH_CONTROL				(0x28A0U)
#define NPU_SYS_CMH_CONTROL				(0x28A8U)
#define NPU_SYS_AMH_CONTROL				(0x28B0U)
#define NPU_SYS_OMH_CONTROL				(0x28B8U)
#define NPU_SYS_ELEMENTOPS_MH_CONTROL			(0x28C0U)
#define NPU_SYS_MM_MH_CONTROL				(0x28C8U)

#define NPU_SYS_H0_MEM_SIZE				(0x28D8U)
#define NPU_SYS_H0_OCM_ADDR				(0x2810U)
#define NPU_SYS_H0_OCM_SIZE				(0x2818U)

#define NPU_SYS_MEM_WDT_CM				(0x2998U)
#define NPU_SYS_MEM_WDT_CTRL				(0x29A0U)
#define NPU_SYS_HWDT_CTRL				(0x29A8U)
#define NPU_SYS_HWDT_CM					(0x29B0U)
#define NPU_SYS_IDLE_HYSTERESIS_COUNT			(0x29C0U)
#define NPU_SYS_SOCIF_WAKEUP_ENABLE			(0x29C8U)

#define NPU_SYS_RESET_CLK_CTRL				(0x29D0U)
#define NPU_SYS_CLK_CTRL0				(0x29D8U)
#define NPU_SYS_AXI_EXACCESS				(0x29E8U)
#define NPU_SYS_REGBANK_REQUEST_INVALID			(0x29F0U)
#define NPU_SYS_CMD_PRIORITY_LIMITS_LEGACY		(0x2900U)
#define NPU_SYS_CMD_SECURITY_CONTROL			(0x2908U)
#define NPU_SYS_ARB_STALL_RATIO				(0x2A80U)

#define NPU_SYS_DATAPATH_STALL_RFE			(0x2A88U)
#define NPU_SYS_DATAPATH_STALL_RBE			(0x2A90U)
#define NPU_SYS_ARB_MP					(0x2A98U)

#define NPU_SYS_MMU_PSIZE_RONE				(0xEBD0U)
#define NPU_SYS_MMU_PSIZE_RTWO				(0xEBD8U)
#define NPU_SYS_MMU_PSIZE_RTHREE			(0xEBE0U)
#define NPU_SYS_MMU_PSIZE_RFOUR				(0xEBE8U)

#define NPU_SYS_MEM_CTRL				(0xEA80U)
#define NPU_SYS_MEM_FAULT_STOP_CTRL			(0xEAC8U)
#define NPU_SYS_ACE_QOS_CTRL				(0xEB90U)
#define NPU_SYS_ACE_PRI_MAP_CTRL			(0xEB98U)
#define NPU_SYS_ACE_CTRL				(0xEBA0U)
#define NPU_SYS_ACE_STATUS				(0xEBB0U)

#define NPU_SYS_L1_GLB_CTRL				(0xEC80U)
#define NPU_SYS_CONTEXT_MAPPING2			(0xF808U)
#define NPU_SYS_CONTEXT_MAPPING3			(0xF810U)
#define NPU_SYS_MEM_FIX					(0xF858U)
#define NPU_SYS_PWR_MAN_HYSTERESIS			(0xF980U)

#define NPU_CH0_CONTROL					(0x10880U)
#define NPU_CH0_STATUS					(0x10888U)

#define NPU_CH0_CMD_BASE_ADDRESS			(0x108A0U)
#define NPU_CH0_ADDR_USED				(0x108B8U)
#define NPU_CH0_ADDR0					(0x108C0U)
#define NPU_CH0_ADDR1					(0x108C8U)
#define NPU_CH0_ADDR2					(0x108D0U)
#define NPU_CH0_ADDR3					(0x108D8U)
#define NPU_CH0_ADDR4					(0x108E0U)
#define NPU_CH0_ADDR5					(0x108E8U)
#define NPU_CH0_ADDR6					(0x108F0U)
#define NPU_CH0_ADDR7					(0x108F8U)
#define NPU_CH0_WRITEBACK_CONTROL			(0x10800U)
#define NPU_CH0_VHA_EVENT_ENABLE			(0x10808U)
#define NPU_CH0_VHA_EVENT_STATUS			(0x10810U)
#define NPU_CH0_VHA_EVENT_CLEAR				(0x10818U)
#define NPU_CH0_CRC_CONTROL				(0x10980U)
#define NPU_CH0_CRC_ADDRESS				(0x10988U)
#define NPU_CH0_DEBUG_ADDRESS				(0x10990U)
#define NPU_CH0_DEBUG_SIZE				(0x10998U)
#define NPU_CH0_DEBUG_CONTROL				(0x109A0U)
#define NPU_CH0_DEBUG_STATUS				(0x109A8U)
#define NPU_CH0_PRELOAD_CONTROL				(0x109B0U)
#define NPU_CH0_ADDR8					(0x109C0U)
#define NPU_CH0_ADDR9					(0x109C8U)
#define NPU_CH0_ADDR10					(0x109D0U)
#define NPU_CH0_ADDR11					(0x109D8U)
#define NPU_CH0_ADDR12					(0x109E0U)
#define NPU_CH0_ADDR13					(0x109E8U)
#define NPU_CH0_ADDR14					(0x109F0U)
#define NPU_CH0_ADDR15					(0x109F8U)

#define NPU_CH0_PERFORMANCE				(0x10920U)
#define NPU_CH0_MMU_CTRL_INVAL				(0x1E880U)
#define NPU_CH0_MMU_MAPPING_CONTEXT			(0x1E888U)
#define NPU_CH0_MMU_MAPPING_ADDR			(0x1E890U)
#define NPU_CH0_MMU_ERR_S1				(0x1E898U)
#define NPU_CH0_MMU_ERR_S2				(0x1E8A0U)
#define NPU_CH0_MMU_CTRL_BS				(0x1E8C0U)

#define MMU_CTRL_BYPASS_EN				(0X1U)
#define MMU_CTRL_BYPASS_DISABLE				(0X0U)
#define MMU_CTRL_ALL_CTX_BIT				(11U)
#define MMU_CTRL_ALL_CTX_EN				(0X00800U)
#define MMU_CTRL_CTX_SHIFT				(3)		/* 3-10bit */
#define MMU_CTRL_INVAL_PC				(0X0004U)
#define MMU_CTRL_INVAL_PD				(0X0002U)
#define MMU_CTRL_INVAL_PT				(0X0001U)

#define MMU_FS1_LEVEL_SHIFT			(62U)
#define MMU_FS1_LEVEL_MSK			(0X3U)
#define MMU_FS1_REQ_ID_SHIFT			(56U)
#define MMU_FS1_REQ_ID_MSK			(0X7FU)
#define MMU_FS1_CONTEXT_SHIFT			(48U)
#define MMU_FS1_CONTEXT_MSK			(0XFFU)
#define MMU_FS1_ADDRESS_SHIFT			(4U)
#define MMU_FS1_ADDRESS_MSK			(0XFFFFFFFFFFFU)
#define MMU_FS1_RNW_SHIFT			(3U)
#define MMU_FS1_RNW_MSK				(0X1)
#define MMU_FS1_TYPE_SHIFT			(1U)
#define MMU_FS1_TYPE_MSK			(0X3U)
#define MMU_FS1_FAULT_SHIFT			(0U)
#define MMU_FS1_FAULT_MSK			(0X1)

#define MMU_FS2_WRITEBACK_SHIFT		(29U)
#define MMU_FS2_WRITEBACK_MSK		(0X1U)
#define MMU_FS2_CLEANUNIQUE_SHIFT	(28U)
#define MMU_FS2_CLEANUNIQUE_MSK		(0X1U)
#define MMU_FS2_BANK_SHIFT		(24U)
#define MMU_FS2_BANK_MSK		(0XFU)
#define MMU_FS2_TLB_ENTRY_SHIFT		(16U)
#define MMU_FS2_TLB_ENTRY_MSK		(0XFFU)
#define MMU_FS2_FBM_FAULT_SHIFT		(10U)
#define MMU_FS2_FBM_FAULT_MSK		(0X1)
#define MMU_FS2_BIF_ID_SHIFT		(0U)
#define MMU_FS2_BIF_ID_MSK		(0X3FFU)

#define MMU_PS_CONFIG_SHIFT		(38U)
#define MMU_PS_END_ADDR_SHIFT		(19U)
#define MMU_PS_BASE_ADDR_SHIFT		(0U)
#define MMU_PS_ADDR_ALIGNSHIFT		(21U)
#define MMU_PS_END_ADDR_DELT_SHIFT	(21 - 19)

#define SYS_CLOCK_AUTO	0x20
#define MAIN_CLOCK_AUTO	0xA2AA2AAA2A000220

#define NPU_SOFT_RESET_CONFIG	0xC0000107
#define NPU_HW_BE_READY			0x200000
/* 100ms @800MHz */
#define NPU_HL_WDT_CYCLES		0xfffffff
/* 1ms @800MHz MEM*/
#define NPU_MEM_WDT_CYCLES		0xffffffff

#define NPU_HW_START_EN			0x1

#define NPU_INFERENCE_COMPLETE_EVENT	0x1
#define NPU_INFERENCT_ERR_EVENT		0x2
#define NPU_MEM_WDT_EVENT		0x8
#define NPU_WDT_EVENT			0x80008
#define NPU_AXI_EVENT			0x40000
#define NPU_MMU_EVENT			0x10000
#define NPU_ERR_EVENT			0x100000
#define NPU_ALL_EVENT		(NPU_INFERENCE_COMPLETE_EVENT | NPU_INFERENCT_ERR_EVENT | \
							NPU_AXI_EVENT | NPU_MMU_EVENT | \
							NPU_WDT_EVENT | NPU_ERR_EVENT)

#define NPU_PRE_CBUF		0x10
#define NPU_PRE_RD_256		0x01000000
#define NPU_PRE_WR_256		0x00200000
#define NPU_PRELOAD_CFG		(NPU_PRE_CBUF | NPU_PRE_RD_256 | NPU_PRE_WR_256)

#endif /* __PHYTIUM_NPU_LEOPARD_REG_H__ */
